CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more function blocks connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms PLD and programmable logic device include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
PLDs and other types of ICs often incorporate various types of memory, such as static random access memory (SRAM) and other types of memory. SRAM is used in a wide variety of ICs, a six-transistor CMOS cell being a common design. A six-transistor CMOS SRAM cell uses cross-coupled CMOS pairs to hold opposite binary values (commonly called Q and Q-bar), which are read by accessing the SRAM cell through access transistors controlled by a word line. The values are provided to bit lines, and read using differential techniques that are well known in the art of SRAM operation.
SRAM circuits have READ and WRITE performance margins to insure the stored data values are accurate. These READ/WRITE margins depend on several factors, such as the operating voltage of the circuit and the node technology used to design and fabricate the IC (for example, 90 nm, 65 nm, or 45 nm node technology).
At low operating voltages (e.g., VCC<1.2V), the NMOS pull-down transistors in the CMOS pairs have a higher drain saturation current than the PMOS pull-up transistors. At small (<90 nm) technologies and low operating voltages, a ratio of IDsat N/IDsat P (IDsat ratio) of about four to five may be required for reliable operation or even higher in some applications. That is, the saturated current through the NMOS pull-down transistors is about four to five times, and in some applications more than ten times, greater than the saturated current through the PMOS pull-up transistors.
The natural IDsat ratio is not sufficient for small node technologies, and several techniques have been developed to increase the IDsat ratio. One approach is to make the NMOS pull-down transistors wider (i.e., design them to have a longer gate width), which increases current; however, it also increases the size of the SRAM memory cell, which is undesirable. Another approach is to make the gate length (i.e., the dimension between the source and drain) of the PMOS pull-up transistors longer, which reduces the saturated current through the PMOS devices; however, this also increases cell area.
Although the increases to SRAM cell sizes may seem small, the cumulative effect of techniques applied to each individual SRAM cell can be quite significant.
Another approach has been to increase the threshold voltage for the PMOS pull-up transistors or otherwise weaken the PMOS transistors (e.g., by modifying the drain/source doping or channel stress), which lowers the saturated current thorough the PMOS device and hence increases the IDsat ratio. These approaches typically add additional masking and processing steps, as increasing the threshold voltage of PMOS devices used elsewhere in the IC (e.g., in logic circuits) is generally undesirable.
Improving the IDsat ratio of SRAM cells in memory arrays that avoid the disadvantages of the prior art are desirable.